Good morning everyone, got my hands on a super pang board from Italy, turned out to be a bootleg. From the look of it it's set 1. Thing is, the silkscreen matches set 2 namings. What i mean, in spangbl the order is
IC17.1, IC18.2, IC19.3 while my board has IC19.1, IC18.2, IC2.3.
This should be fixable by just experimenting with the ROMs but both won't work, which in turn made me look into it a bit further. The GAL16V8 next to the CPU is dead. Does anybody have the jed file for the gal?
image bin of the board.
Benvenuto Ospite,
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Super Pang bootleg GAL
-
DigDug
- Moderatore
- Messaggi: 3495
- Iscritto il: 23/07/2005, 19:24
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- Città: Rimini
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Re: Super Pang bootleg GAL
Ho la stessa scheda, non funzionante, dà schermo bianco.
Anche io ho sostituito quella gal, che scaldava troppo, ma non è cambiato nulla.
https://wiki.pldarchive.co.uk/index.php ... bootleg%29
Anche io ho sostituito quella gal, che scaldava troppo, ma non è cambiato nulla.
https://wiki.pldarchive.co.uk/index.php ... bootleg%29
Re: Super Pang bootleg GAL
Yes, i have already tried this GAL but code doesnt match the pins.
1) Rom selection on GAL goes like this:
o15 (pin 15) = /A15 & i7 & i11 (drives IC18 /OE (reset window 0000–7FFF)).
o16 (pin 16) = A15’=1 & /A14 & i7 & i11 (drives IC19 /OE (8000–BFFF)).
On the contrary, my board is selecting by /CE: IC18 /CE and IC19 /CE are shorted together and tied to IC4 pin 16
2) CPU Fetch polarity
ON GAL during the first fetch (A15=0), o15 must go LOW to enable the ROM that holds the first byte.
On my board /CE (from IC4 pin16) goes HIGH at M1(falling), i.e., disables both ROMs when the CPU tries to read.
3) /OE routing topology
On IC4 two distinct active-LOW enables (o15→OE18, o16→OE19).
On my board IC18 /OE <-> 74LS368 pin6 (input), IC19 /OE <-> 74LS368 pin7 (inverted output), i.e. OEs are forced complementary from a single net, not independently driven by o15/o16.
4) Input mapping match both.
1) Rom selection on GAL goes like this:
o15 (pin 15) = /A15 & i7 & i11 (drives IC18 /OE (reset window 0000–7FFF)).
o16 (pin 16) = A15’=1 & /A14 & i7 & i11 (drives IC19 /OE (8000–BFFF)).
On the contrary, my board is selecting by /CE: IC18 /CE and IC19 /CE are shorted together and tied to IC4 pin 16
2) CPU Fetch polarity
ON GAL during the first fetch (A15=0), o15 must go LOW to enable the ROM that holds the first byte.
On my board /CE (from IC4 pin16) goes HIGH at M1(falling), i.e., disables both ROMs when the CPU tries to read.
3) /OE routing topology
On IC4 two distinct active-LOW enables (o15→OE18, o16→OE19).
On my board IC18 /OE <-> 74LS368 pin6 (input), IC19 /OE <-> 74LS368 pin7 (inverted output), i.e. OEs are forced complementary from a single net, not independently driven by o15/o16.
4) Input mapping match both.